#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bade208b |
|
30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
4d4222d0 |
|
01-Sep-2021 |
Zong Li <zong.li@sifive.com> |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
9edefc27 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some cache and MMU functions out of common.h These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
52923c6d |
|
06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
#
62a09ad5 |
|
22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f74c416e |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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52923c6d |
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06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
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62a09ad5 |
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22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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f74c416e |
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03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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c9056653 |
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03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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52923c6d |
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06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
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#
62a09ad5 |
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22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f74c416e |
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03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c9056653 |
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03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
52923c6d |
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06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
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#
62a09ad5 |
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22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f74c416e |
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03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c9056653 |
|
03-Jan-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
52923c6d |
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06-Nov-2018 |
Rick Chen <rick@andestech.com> |
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
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#
62a09ad5 |
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22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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8bbb2909 |
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25-Dec-2017 |
Rick Chen <rick@andestech.com> |
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
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