#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
d1b24a61 |
|
16-Nov-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
04b2123b |
|
11-Oct-2023 |
Randolph <randolph@andestech.com> |
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
bc35b49a |
|
04-Jul-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andes_plicsw: Fix IPI during OpenSBI invocation On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
a5dfa3b8 |
|
25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
a5dfa3b8 |
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25-Oct-2022 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
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