| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
| #
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|