#
0b9441ae |
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12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
d768dd88 |
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12-Aug-2023 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
common: return type board_get_usable_ram_top board_get_usable_ram_top() returns a physical address that is stored in gd->ram_top. The return type of the function should be phys_addr_t like the current type of gd->ram_top. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
049704f8 |
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09-Sep-2022 |
Pali Rohár <pali@kernel.org> |
board_f: Fix types for board_get_usable_ram_top() Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") changed type of ram_top member from ulong to phys_addr_t but did not changed types in board_get_usable_ram_top() function which returns value for ram_top. So change ulong to phys_addr_t type also in board_get_usable_ram_top() signature and implementations. Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
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2ae80437 |
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15-Feb-2021 |
Tom Rini <trini@konsulko.com> |
Merge branch '2021-02-02-drop-asm_global_data-when-unused' - Merge the patch to take <asm/global_data.h> out of <common.h>
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#
85c714d8 |
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31-Jan-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Adjust board_get_usable_ram_top() for 32-bit When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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7c45fc98 |
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29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540 Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d768dd88 |
|
12-Aug-2023 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
common: return type board_get_usable_ram_top board_get_usable_ram_top() returns a physical address that is stored in gd->ram_top. The return type of the function should be phys_addr_t like the current type of gd->ram_top. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
049704f8 |
|
09-Sep-2022 |
Pali Rohár <pali@kernel.org> |
board_f: Fix types for board_get_usable_ram_top() Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") changed type of ram_top member from ulong to phys_addr_t but did not changed types in board_get_usable_ram_top() function which returns value for ram_top. So change ulong to phys_addr_t type also in board_get_usable_ram_top() signature and implementations. Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
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2ae80437 |
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15-Feb-2021 |
Tom Rini <trini@konsulko.com> |
Merge branch '2021-02-02-drop-asm_global_data-when-unused' - Merge the patch to take <asm/global_data.h> out of <common.h>
|
#
85c714d8 |
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31-Jan-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Adjust board_get_usable_ram_top() for 32-bit When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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7c45fc98 |
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29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540 Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
049704f8 |
|
09-Sep-2022 |
Pali Rohár <pali@kernel.org> |
board_f: Fix types for board_get_usable_ram_top() Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") changed type of ram_top member from ulong to phys_addr_t but did not changed types in board_get_usable_ram_top() function which returns value for ram_top. So change ulong to phys_addr_t type also in board_get_usable_ram_top() signature and implementations. Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2ae80437 |
|
15-Feb-2021 |
Tom Rini <trini@konsulko.com> |
Merge branch '2021-02-02-drop-asm_global_data-when-unused' - Merge the patch to take <asm/global_data.h> out of <common.h>
|
#
85c714d8 |
|
31-Jan-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Adjust board_get_usable_ram_top() for 32-bit When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540 Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2ae80437 |
|
15-Feb-2021 |
Tom Rini <trini@konsulko.com> |
Merge branch '2021-02-02-drop-asm_global_data-when-unused' - Merge the patch to take <asm/global_data.h> out of <common.h>
|
#
85c714d8 |
|
31-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
riscv: Adjust board_get_usable_ram_top() for 32-bit When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540 Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
85c714d8 |
|
31-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
riscv: Adjust board_get_usable_ram_top() for 32-bit When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com> |
#
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540 Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7c45fc98 |
|
29-May-2020 |
Pragnesh Patel <pragnesh.patel@sifive.com> |
riscv: cpu: fu540: Add support for cpu fu540 Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |